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- E. Taylor and J. Fortes, “Device variability impact on logic gate failure rates,” GOMAC 2007.
- E. Taylor, J. Han, J. Fortes, “Towards the accurate and efficient reliability modeling of nanoelectronic circuits,” Conference on Nanotechnology 2006.
- E. Taylor, J. Han, J. Fortes, “An investigation into the maximum tolerable error rate of majority gates for reliable computation,” NanoArch 2006.
- J. Han, E. Taylor, J. Gao and J. Fortes, “Faults, error bounds and reliability of nanoelectronic circuits,” ASAP 2005.
- J. Han, E. Taylor, J. Gao and J. Fortes, “Reliability modeling of nanoelectronic circuits,” Conference on Nanotechnology 2005.