Research Projects

Title: Quantitative analysis of gene regulation in the neuronal stress response

Principal researchers: Erin Taylor, William Ogle, Philip Barish

Summary:

Glucocortcoids serve an important function in the neuronal response to stress.  However, an excess of these adrenal steroid hormones compromises the ability of hippocampal neurons to survive neurological damage.  In this project, we are experimenting with several novel genetic constructs that alter the neuronal response to glucocortcoids in order to improve cell survival.  A quantitative analysis of our constructed genetic regulatory network will be performed.

Title: Improving Timer Accuracy in Virtualized Systems for Real-Time Computing

Principal researchers: Erin Taylor, Mauricio Tsugawa, and Jose Fortes (ACIS-UF)

Summary:
Virtual machines (VMs) offer improved compatibility, isolation, reliability and security for computing applications. Unfortunately, they have difficulty maintaining accurate measures of time. In a traditional computer with a single operating system, time is kept accurately though the use of hardware timer interrupts. In systems of VMs, however, a given VM may not be running on a CPU when a timer interrupt occurs and so its measure of time will not be updated correctly. As a result, timekeeping in VMs is inaccurate. This fact makes utilizing VMs for real-time computing a challenge. The goal of this work is to improve the timing accuracy of VMs in order to improve their applicability to real-time computing. This will be done by reducing timing error and meeting computing deadlines through the use of time-space processor affinity.

Time-space processor affinity is a controllable parameter that denotes how a processor is preferentially assigned and scheduled to run a VM. Because a VM’s timer accuracy is proportional to the amount of time it spends on a processor, we can adjust processor affinity to give specific VMs more time on a CPU resulting in more accurate timekeeping. There are several different strategies for setting affinity that may be useful in maintaining high timer accuracy for real-time computing. The best strategy will depend on the number of high-priority VMs in the system as well as available CPUs. This project will explore these different strategies and, based on the best model, develop an autonomic affinity manager that will set VM affinity according to priority and real-time deadlines.

In newer models of real-time systems, constraints are defined using time intervals rather than discrete timestamps. Timing inaccuracies in VMs can be modeled using this interval-based approach where the size of the interval is proportional to the timing error. Adjusting affinity will reduce the uncertainty in timing and increase the probability of meeting real-time deadlines.

The first step in this project will be to determine the best strategy for assigning processor affinity in order to meet real-time deadlines and then to design an autonomic affinity manager to implement these affinity assignments. We will also model timing inaccuracies with interval-based timing constraints and use this model to determine the feasibility of real-time demands.

Title: Reliability modeling of nanoelectronic circuits

Principal researchers: Erin Taylor and José A.B. Fortes (ACIS –UF)

Current collaborators: N/A

Past collaborators: Jie Han (ACIS-UF), Jianbo Gao (UF)

Summary:

Extensive efforts are being made to develop nanoelectronic devices implemented in nanoscale CMOS and in novel nanotechnologies such as quantum-dot cellular automata (QCA), single-electron tunneling devices (SET), carbon nanotubes, and molecular electronics. At the nanoscale, precise control over the fabrication of devices will be extremely difficult, and this will lead to high defect rates and process variability, both of which will have a negative impact on the correct functioning and reliability of devices. Thus, nanoscale computing will have to deal with probabilistic and unreliable behavior of future nano-devices.

This concern for the reliability of nanoelectronics has motivated efforts to develop reliability evaluation techniques based on the probabilistic nature of future nanoscale computation. Our project contributes to this work by developing a method which uses probabilistic gate models (PGMs) for reliability estimation. The probabilistic nature of this method makes it applicable to the analysis of logic circuits implemented with any nanotechnology.

References:

1. Jie Han, Erin Taylor, Jianbo Gao and Jose Fortes ‘Reliability Modeling of Nanoelectronic Circuits’. IEEE Conference on Nanotechnology, 07/2005.

2. Jie Han, Erin Taylor, Jianbo Gao and Jose Fortes ‘Faults, error bounds and reliability of nanoelectronic circuits’. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) , 07/2005.

3. Erin Taylor, Jie Han, Jose Fortes ‘Towards the accurate and efficient reliability modeling of nanoelectronic circuits’. IEEE Conference on Nanotechnology, 06/2006.

Title: Device variability impact on logic gate failure rates

Principal researchers: Erin Taylor and José A.B. Fortes (ACIS –UF)

Current collaborators: Julie Dewberry (ACIS-UF)

Past collaborators: N/A

Summary:

Well-established reliability models indicate that the failure rates of scaled CMOS will continue to increase due to manufacturing variability and wear-out caused by negative bias temperature instability and hot carrier injection effects. Thus, the reliability of future devices is a critical concern for circuit designers. In order to predict the feasibility and reduce the cost of these new, fault-prone structures, techniques to efficiently determine circuit reliability are needed. To this end, we have introduced in our previous projects a probabilistic gate-level model based on stuck-at and inversion faults to evaluate circuit reliability and derive fundamental error bounds for logic gates. In this work, we utilize recent studies on transistor variability in emerging silicon devices to confirm the validity of these fault models as well as to determine realistic fault rates. We show that the failure mechanisms and error rates that we derive can be incorporated into our probabilistic gate model framework, and therefore, our method of reliability analysis can potentially be used in the design and manufacturing of circuits to reduce testing time and indicate the need for fault mitigation techniques.

References:

1. Erin Taylor and Jose Fortes ‘Device variability impact on logic gate failure rates’. Government Microcircuit Applications and Critical Technology Conference (GOMAC), 03/2007.

2. Kufluoglu, H. and M.A. Alam, “A computational model of NBTI and hot carrier injection time-exponents for MOSFET reliability,” J. Computational Electronics, 2004, Vol. 3, pp165-169.

Title: Investigating logic gate error bounds

Principal researchers: Erin Taylor and José A.B. Fortes (ACIS –UF)

Current collaborators: N/A

Past collaborators: Jie Han (ACIS-UF), Jianbo Gao (UF)

Summary:

As CMOS devices reach their fundamental physical limits, they will increasingly suffer from short channel effects, doping fluctuations, and other phenomena which will negatively impact their reliability. These future limitations of CMOS have led many to consider novel nanometer-scale devices that are hoped to have faster switching speeds, lower power consumption, and better scaling characteristics.

For devices at the nanometer scale, however, reliability will be adversely affected by background charges, dynamic variations in the operating environment such as temperature fluctuations, and manufacturing defects due to the inability to precisely control the fabrication process. Although many fault tolerant architectures for nanoelectronics have been proposed, these devices will still have to achieve a certain level of inherent reliability in order to be cost-effective. It is therefore pertinent to consider the bounds on this reliability. In this work, we have developed an approach based on probabilistic models of unreliable logic gates. These reliability models are expressed in terms of nonlinear mapping functions from which bifurcation analysis is used to obtain fundamental error bounds for general logic gates.

References:

1. Jie Han, Erin Taylor, Jianbo Gao and Jose Fortes ‘Faults, error bounds and reliability of nanoelectronic circuits’. IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) , 07/2005.

2. Erin Taylor, Jie Han, Jose Fortes ‘An investigation into the maximum tolerable error rate of majority gates for reliable computation’. International Workshop on Defect and Fault Tolerance Nanoscale Architectures (NanoArch), 06/2006.

3. J. von Neumann, “Probabilistic logics and the synthesis of reliable organisms from unreliable components,” Automata Studies, Shannon C.E. & McCarthy J., eds., Princeton University Press, Princeton N.J. pp. 43-98, 1956.

4. B. Hajek and T. Weller, “On the maximum tolerable noise for reliable computation by formulas.” IEEE Trans. On Info. Theory, 37, 2, 1991.